DIGITAL FILTER IMPLEMENTATION BY USING MICROPROCESSORS
Abstract
THIS THESIS DEALS WITH THE REAL TIME IMPLEMENTATION OF VARIOUS DIGITAL FILTER STRUCTURES BY USING DIFFERENT TYPES OF SUITABLY ENHANCED PROGRAMMABLE HARDWARE. MORE SPECIFICALLY, FILTER STRUCTURES SUCH AS WAVE DIGITAL LADDER AND LATTICE FILTERS, STATE SPACE FILTERS AND FIR FILTERS, ARE PROPERLY MODIFIED IN ORDER TO EXPLOIT EFFICIENTLY, BOTH IN ACCURACY AND IN SPEED, THE HARDWARE WHICH IS PROPOSED FOR THIS PURPOSE. IN THE CASE WHERE AN 8-BIT OR 16-BIT GENERAL PURPOSE MICROPROCESSOR IS USED IN DIGITAL FILTERING THE ADOPTION OF EXTERNAL HARDWARE IS PROPOSED, IN ORDER TO BROADEN THE SIGNAL BANDWIDTH THAT CAN BE PROCESSED BY THE DESIGNED SYSTEMS. THE PROPOSED HARDWARE IS DESIGNED AROUND FAST PARALLEL MULTIPLIERS OR MULTIPLIER-ACCUMULATORS IN A RATHER EFFECTIVE WAY. IN ORDER TO IMPLEMENTA DIGITAL VARIABLE FILTER, A NEW SCHEME IS PROPOSED WHICH MAKES USE OF A DSP AND AN 8-BIT MP IN A MASTER-SLAVE ARCHITECTURE.
![]() | Download full text in PDF format (12.36 MB)
(Available only to registered users)
|
All items in National Archive of Phd theses are protected by copyright.
|
Usage statistics
VIEWS
Concern the unique Ph.D. Thesis' views for the period 07/2018 - 07/2023.
Source: Google Analytics.
Source: Google Analytics.
ONLINE READER
Concern the online reader's opening for the period 07/2018 - 07/2023.
Source: Google Analytics.
Source: Google Analytics.
DOWNLOADS
Concern all downloads of this Ph.D. Thesis' digital file.
Source: National Archive of Ph.D. Theses.
Source: National Archive of Ph.D. Theses.
USERS
Concern all registered users of National Archive of Ph.D. Theses who have interacted with this Ph.D. Thesis. Mostly, it concerns downloads.
Source: National Archive of Ph.D. Theses.
Source: National Archive of Ph.D. Theses.






